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origen_verilog
A parser and generator for Verilog (IEEE 1364)
Total
Ranking: 36,546 of 186,954
Downloads: 32,823
Daily
Ranking: 19,316 of 186,947
Downloads: 17
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| Rank | Downloads | Name |
|---|---|---|
| 26,873 | 50,098 | origen_sim |
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