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origen_verilog
A parser and generator for Verilog (IEEE 1364)
Total
Ranking: 36,437 of 180,477
Downloads: 28,913
Daily
Ranking: 50,107 of 180,469
Downloads: 0
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| Rank | Downloads | Name |
|---|---|---|
| 26,085 | 45,314 | origen_sim |
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