Categories: Automation [Edit]
rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to control and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Total
Ranking: 15,975 of 186,698
Downloads: 111,583
Daily
Ranking: 15,812 of 186,685
Downloads: 18
Downloads Trends
Ranking Trends
Num of Versions Trends
Popular Versions (Major)
Popular Versions (Major.Minor)
Depended by
Rank | Downloads | Name |
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Depends on
Rank | Downloads | Name |
---|---|---|
23,091 | 61,629 | rggen-core |
24,221 | 57,626 | rggen-systemverilog |
28,959 | 44,496 | rggen-default-register-map |
29,424 | 43,465 | rggen-markdown |
31,019 | 40,480 | rggen-spreadsheet-loader |
59,671 | 16,792 | rggen-c-header |
Owners
# | Gravatar | Handle |
---|---|---|
1 | taichi |