Categories: Automation [Edit]
rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Total
Ranking: 16,448 of 180,507
Downloads: 89,472
Daily
Ranking: 10,985 of 180,487
Downloads: 86
Downloads Trends
Ranking Trends
Num of Versions Trends
Popular Versions (Major)
Popular Versions (Major.Minor)
Depended by
Rank | Downloads | Name |
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Depends on
Rank | Downloads | Name |
---|---|---|
27,729 | 41,662 | rggen-systemverilog |
28,074 | 40,951 | rggen-core |
35,422 | 30,058 | rggen-default-register-map |
38,686 | 26,771 | rggen-spreadsheet-loader |
39,184 | 26,355 | rggen-markdown |
104,965 | 6,228 | rggen-c-header |
Owners
# | Gravatar | Handle |
---|---|---|
1 | taichi |