Categories: Automation [Edit]

rggen

https://rubygems.org/gems/rggen
https://github.com/rggen/rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Total

Ranking: 16,010 of 186,947
Downloads: 112,340

Daily

Ranking: 15,752 of 186,938
Downloads: 42

Depended by

RankDownloadsName

Depends on

RankDownloadsName
23,07962,283rggen-core
24,22558,205rggen-systemverilog
28,99544,872rggen-default-register-map
29,38344,039rggen-markdown
30,79841,341rggen-spreadsheet-loader
59,03117,260rggen-c-header

Owners

#GravatarHandle
1icontaichi