Categories: Automation [Edit]

rggen

https://rubygems.org/gems/rggen
https://github.com/rggen/rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Total

Ranking: 15,975 of 186,698
Downloads: 111,583

Daily

Ranking: 15,812 of 186,685
Downloads: 18

Depended by

RankDownloadsName

Depends on

RankDownloadsName
23,09161,629rggen-core
24,22157,626rggen-systemverilog
28,95944,496rggen-default-register-map
29,42443,465rggen-markdown
31,01940,480rggen-spreadsheet-loader
59,67116,792rggen-c-header

Owners

#GravatarHandle
1icontaichi