Categories: Automation [Edit]
rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to control and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Total
Ranking: 16,010 of 186,947
Downloads: 112,340
Daily
Ranking: 15,752 of 186,938
Downloads: 42
Downloads Trends
Ranking Trends
Num of Versions Trends
Popular Versions (Major)
Popular Versions (Major.Minor)
Depended by
Rank | Downloads | Name |
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Depends on
Rank | Downloads | Name |
---|---|---|
23,079 | 62,283 | rggen-core |
24,225 | 58,205 | rggen-systemverilog |
28,995 | 44,872 | rggen-default-register-map |
29,383 | 44,039 | rggen-markdown |
30,798 | 41,341 | rggen-spreadsheet-loader |
59,031 | 17,260 | rggen-c-header |
Owners
# | Gravatar | Handle |
---|---|---|
1 | taichi |