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origen_verilog
A parser and generator for Verilog (IEEE 1364)
Total
Ranking: 35,145 of 196,658
Downloads: 38,951
Daily
Ranking: 60,867 of 196,619
Downloads: 3
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| Rank | Downloads | Name |
|---|---|---|
| 27,670 | 54,492 | origen_sim |
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