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origen_verilog
A parser and generator for Verilog (IEEE 1364)
Total
Ranking: 36,760 of 187,591
Downloads: 33,164
Daily
Ranking: 130,231 of 187,571
Downloads: 5
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| Rank | Downloads | Name |
|---|---|---|
| 27,096 | 50,448 | origen_sim |
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