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origen_verilog
A parser and generator for Verilog (IEEE 1364)
Total
Ranking: 36,202 of 183,107
Downloads: 30,796
Daily
Ranking: 53,556 of 183,092
Downloads: 1
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| Rank | Downloads | Name |
|---|---|---|
| 26,227 | 47,659 | origen_sim |
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