Categories: Automation [Edit]

rggen

https://rubygems.org/gems/rggen
https://github.com/rggen/rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Total

Ranking: 25,299 of 159,838
Downloads: 20,905

Daily

Ranking: 13,263 of 159,806
Downloads: 48

Depended by

RankDownloadsName

Depends on

RankDownloadsName
7442,246,427bundler
71,7075,220rggen-core
71,8275,208rggen-systemverilog
96,0943,153rggen-default-register-map
102,2912,903rggen-markdown
105,1832,764rggen-spreadsheet-loader

Owners

#GravatarHandle
1icontaichi