Categories: Automation [Edit]
rggen
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Total
Ranking: 16,463 of 180,402
Downloads: 88,902
Daily
Ranking: 11,733 of 180,392
Downloads: 57
Downloads Trends
Ranking Trends
Num of Versions Trends
Popular Versions (Major)
Popular Versions (Major.Minor)
Depended by
Rank | Downloads | Name |
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Depends on
Rank | Downloads | Name |
---|---|---|
27,843 | 41,253 | rggen-systemverilog |
28,202 | 40,550 | rggen-core |
35,645 | 29,723 | rggen-default-register-map |
38,988 | 26,443 | rggen-spreadsheet-loader |
39,459 | 26,049 | rggen-markdown |
107,200 | 5,963 | rggen-c-header |
Owners
# | Gravatar | Handle |
---|---|---|
1 | taichi |