1 | 36,767 | 28,864 | vhdl_tb | A simple testbench generator for VHDL |
2 | 43,176 | 41,906 | crokus | Crokus is a parser for a subset of C language. It has been use for teaching purposes an... |
3 | 54,004 | 21,702 | vertigo_vhdl | A Ruby handwritten VHDL parser and utilities |
4 | 54,392 | 52,232 | vhdl_help | A simple snippets generator for VHDL on linux command line |
5 | 105,778 | 79,620 | astrapi | Starting from the metamodel of a DSL (abstract classes and their relationship), Astrapi... |
6 | 108,462 | 52,232 | xyp | xyp is a simple 2D graphics plotter |
7 | 130,459 | 68,264 | rtl_circuit | simple digital circuit modeling, with hierarchy and graphviz output |
8 | 141,834 | 73,587 | sexpir | sexpir is a sexp-based interchange format for RTL design |
9 | 148,083 | 86,482 | scrag | Helps me design my DSL tools quicker |
10 | 170,647 | 131,144 | ruby_rtl | ruby_rtl is a simple DSL for HW(RTL) design |
11 | 174,719 | 104,717 | reggae_eda | Generates a bus-based VHDL IP from a register-map specification. An UART-bus master can... |
12 | 183,690 | 117,132 | mir_processing | MIR means 'Manipulations d'Images en Ruby |