Jcll's Gems

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#Total RankDaily RankNameSummary
137,36776,154vhdl_tbA simple testbench generator for VHDL
242,96459,190crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
352,84359,190vertigo_vhdlA Ruby handwritten VHDL parser and utilities
454,940111,095vhdl_helpA simple snippets generator for VHDL on linux command line
5106,813111,095astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
6106,813111,095xypxyp is a simple 2D graphics plotter
7127,051111,095rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8138,929111,095sexpirsexpir is a sexp-based interchange format for RTL design
9146,069111,095scragHelps me design my DSL tools quicker
10169,30576,154ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11175,992111,095reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12186,157111,095mir_processingMIR means 'Manipulations d'Images en Ruby