Jcll's Gems

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#Total RankDaily RankNameSummary
136,83841,609vhdl_tbA simple testbench generator for VHDL
242,63855,176crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
353,37029,296vertigo_vhdlA Ruby handwritten VHDL parser and utilities
454,47355,176vhdl_helpA simple snippets generator for VHDL on linux command line
5106,02555,176astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
6106,35255,176xypxyp is a simple 2D graphics plotter
7127,38241,609rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8139,14255,176sexpirsexpir is a sexp-based interchange format for RTL design
9146,63255,176scragHelps me design my DSL tools quicker
10168,90655,176ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11175,24655,176reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12184,67855,176mir_processingMIR means 'Manipulations d'Images en Ruby