Jcll's Gems

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#Total RankDaily RankNameSummary
136,87217,183vhdl_tbA simple testbench generator for VHDL
242,65166,944crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
353,29521,624vertigo_vhdlA Ruby handwritten VHDL parser and utilities
454,50024,096vhdl_helpA simple snippets generator for VHDL on linux command line
5106,06386,810astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
6106,34755,181xypxyp is a simple 2D graphics plotter
7127,090121,766rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8138,94886,810sexpirsexpir is a sexp-based interchange format for RTL design
9146,406121,766scragHelps me design my DSL tools quicker
10168,942121,766ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11175,28686,810reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12184,77186,810mir_processingMIR means 'Manipulations d'Images en Ruby