Jcll's Gems

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#Total RankDaily RankNameSummary
137,26740,201vhdl_tbA simple testbench generator for VHDL
242,95467,648crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
352,87918,244vertigo_vhdlA Ruby handwritten VHDL parser and utilities
454,81823,905vhdl_helpA simple snippets generator for VHDL on linux command line
5106,60454,810astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
6106,66729,931xypxyp is a simple 2D graphics plotter
7127,00289,809rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8138,90689,809sexpirsexpir is a sexp-based interchange format for RTL design
9146,079127,038scragHelps me design my DSL tools quicker
10169,220127,038ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11175,825127,038reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12185,865127,038mir_processingMIR means 'Manipulations d'Images en Ruby