| 1 | 36,922 | 47,186 | vhdl_tb | A simple testbench generator for VHDL |
| 2 | 42,696 | 36,487 | crokus | Crokus is a parser for a subset of C language. It has been use for teaching purposes an... |
| 3 | 53,289 | 47,186 | vertigo_vhdl | A Ruby handwritten VHDL parser and utilities |
| 4 | 54,544 | 20,567 | vhdl_help | A simple snippets generator for VHDL on linux command line |
| 5 | 106,100 | 47,186 | astrapi | Starting from the metamodel of a DSL (abstract classes and their relationship), Astrapi... |
| 6 | 106,362 | 47,186 | xyp | xyp is a simple 2D graphics plotter |
| 7 | 127,011 | 47,186 | rtl_circuit | simple digital circuit modeling, with hierarchy and graphviz output |
| 8 | 138,808 | 36,487 | sexpir | sexpir is a sexp-based interchange format for RTL design |
| 9 | 146,332 | 79,308 | scrag | Helps me design my DSL tools quicker |
| 10 | 168,948 | 47,186 | ruby_rtl | ruby_rtl is a simple DSL for HW(RTL) design |
| 11 | 175,331 | 47,186 | reggae_eda | Generates a bus-based VHDL IP from a register-map specification. An UART-bus master can... |
| 12 | 184,883 | 79,308 | mir_processing | MIR means 'Manipulations d'Images en Ruby |
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