Jcll's Gems

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#Total RankDaily RankNameSummary
137,40021,259vhdl_tbA simple testbench generator for VHDL
242,99237,505crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
352,70018,231vertigo_vhdlA Ruby handwritten VHDL parser and utilities
454,92923,307vhdl_helpA simple snippets generator for VHDL on linux command line
5106,67131,452xypxyp is a simple 2D graphics plotter
6106,946110,190astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
7126,97859,177rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8138,79476,739sexpirsexpir is a sexp-based interchange format for RTL design
9145,85576,739scragHelps me design my DSL tools quicker
10169,41659,177ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11176,15976,739reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12186,268110,190mir_processingMIR means 'Manipulations d'Images en Ruby