Jcll's Gems

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#Total RankDaily RankNameSummary
137,49146,026vhdl_tbA simple testbench generator for VHDL
243,06769,179crokusCrokus is a parser for a subset of C language. It has been use for teaching purposes an...
352,66554,325vertigo_vhdlA Ruby handwritten VHDL parser and utilities
455,056103,058vhdl_helpA simple snippets generator for VHDL on linux command line
5106,75069,179xypxyp is a simple 2D graphics plotter
6107,11669,179astrapiStarting from the metamodel of a DSL (abstract classes and their relationship), Astrapi...
7126,84869,179rtl_circuitsimple digital circuit modeling, with hierarchy and graphviz output
8138,806103,058sexpirsexpir is a sexp-based interchange format for RTL design
9145,918103,058scragHelps me design my DSL tools quicker
10169,493103,058ruby_rtlruby_rtl is a simple DSL for HW(RTL) design
11176,242103,058reggae_edaGenerates a bus-based VHDL IP from a register-map specification. An UART-bus master can...
12186,543103,058mir_processingMIR means 'Manipulations d'Images en Ruby